In a high-speed data communication application, transmitted data may be modulated into a multi-dimensional bit stream format. In each dimension of the bit stream, a bit pattern for a symbol may be transmitted through one wire or one pair of wires. For example, in the situation where there are four pairs of wires at the transmission side, a number or a symbol represented by one 8-bit data may be coded into four couples of sub-symbols, each one representing an integer from −2, −1, 0, 1, and 2, and each one to be sent through one pair of wires. These four couples of sub-symbols are now representing the one symbol that was originally represented by the two 8-bit data.
At the receiving side, the four couples of sub-symbols will need to be decoded back to the original 8-bit format. However in a high-speed data communication system, these four pairs of sub-symbols may go through different wire delays and may therefore arrive at different clock cycles at a receiver system. Also, the four pairs of wires may be transposed in a transmission channel, causing some pairs of sub-symbols to be swapped.
A receiver system usually processes the bit stream in several stages, including a front-end signal processing stage and a decoding stage. At the front-end signal processing stage, the bit patterns are typically processed one dimension at a time. The results are then forwarded to the decoding stage. A conventional Viterbi decoder typically handles the decoding stage. However, the Viterbi decoder usually requires that the bit patterns in different dimensions be well aligned for the same symbol and the pair-swaps be reordered. This adds complexity to the design of the decoder stage in a receiver system.
Moreover, symbol alignment and pair-swap reordering operations typically require the use of many data buffers. Digital first-in-first-out buffers (“FIFO”) have been used for symbol level data synchronization. However, when multiple pairs of wires are involved, the conventional FIFO structure becomes too simple for the reordering of the pairs of wires, and it cannot perform pair-swap reordering and symbol alignment at the same time. To solve the problem, many FIFO's may operate in parallel to buffer the data. Since the FIFO's are power-hungry and area-consuming components, using many FIFO's for the symbol alignment and pair-swap reordering operations in the receiver system becomes undesirably space demanding and power consuming.